Synopsys jobs - San Jose, CA
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| Jun 01 | Analog IC Designer | Linear Dimensions Semiconductors | Cupertino, CA |
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Linear Dimensions is in desperate need of experienced layout personnel. The job entails supporting electrical engineering staff by laying out analog integrated circuits from... more |
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| Jun 01 | Senior CAD Engineer | I-hire | San Jose, CA |
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in Automated place and route flows (Synopsys ndash; ICCompiler and/or Atoptech Aprisa) Cadence Virtuoso knowledge a plus. Preferably from a CAD background so that the person has... more |
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| Jun 01 | TMM Marketing ANALOG Valley #1422 | Eda Careers | San Jose, CA |
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tools: SpringSoft ADP, Cadence ADE, Synopsys Custom Designer, Hspice, Spectre, Eldo, BDA Analog FastSpice, or other SPICE simulation tool?IC design: analog or custom digital... more |
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| May 29 | MTS CAD Design Engineer | AMD | Sunnyvale, CA |
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design like Cadence First Encounter, Synopsys ICC, or Mentor Sierra Pinnacle is preferred. BS+ 5-7 years, MS+3-5 years or PhD+1year industry experience is preferred. The candidate... more |
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| May 28 | ASIC Developer | Ascent Services Group | San Jose, CA |
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ASICs development tools * Synopsys VCS 80 * Synopsys DC * Synopsys synplicity 12 /tools/synplicity * Cadence-Denali * Cadence Denali_SIM_pcie * Xilinx libraries * LSF lsf_base *... more |
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| May 28 | ASIC Physical Design Engineer | Artisan | San Jose, CA |
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Synopsys Design Compiler/IC Compiler, Cadence EDI or Magma Talus. Strong and detailed understanding of P&R methodology, especially routing algorithms and DRCs. Strong scripting... more |
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| May 25 | Software Quality Engineer | Intel | Santa Clara, CA |
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with EDA tools from vendors like Mentor or Synopsys. We offer a monthly salary of 1.146 EUR before taxes. We are prepared to overpay depending on qualification and job experience... more |
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| May 24 | Physical Design Engineer | LSI | Milpitas, CA |
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such as Magma Talus, Cadence Encounter, or Synopsys IC Compiler. Proficiency in TCL and Perl scripting to achieve higher performance and productivity through automation. High... more |
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| May 24 | Sr Staff Engineer-Verification | CSR | Sunnyvale, CA |
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having experience with either Cadence or Synopsys tools. * Define architecture for given functionality by logical partitioning of the design and interfaces. * Generate and... more |
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| May 23 | Engineer, Sr Principal - IC Design | Broadcom | Sunnyvale, CA |
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computer-aided design tools: P&R tools (synopsys, Cadence, or other leading vendors), ... LVS/DRC tools like Mentor/Calibre, Synopsys/Hercules, etc. Experience with the... more |
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| May 23 | Low-Power RTL ASIC Engineer | Cameron Resources Group | Sunnyvale, CA |
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through silicon bringup Experience with Synopsys or Cadence low-power tools such as UPF: MVRC, MVSIM -or- CPF: Conformal-LP ( CLP ), Power-Aware RTL Compiler Job Requirements:... more |
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| May 22 | Physical Design Engineer - 8+yr exp - 876873693 | San Jose, CA | |
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Clk synthesis, power planning * Expert in Synopsys ICC, Magma Talus, Mentor Olympus, Cadence FE tool set. * Experience in Mentor caliber tools to run Physical verification *... more |
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| May 17 | Design Enablement Engineer | Kore Systems | Milpitas, CA |
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* 3+ years experience in Mentor Calibre, Synopsys ICV and/or other verification languages * 2+ years experience in developing a fill synthesis algorithm * 2+ years experience in... more |
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| May 16 | Sr. ASIC Verification Engineer | Synopsys | Mountain View, CA |
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Responsible for Architecting designing developing and debugging Verification IP software models Highly proficient in the following skill areas middot Design of ASIC Verification... more |
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| May 15 | Senior Physical Design Engineer | Premier Personnel Services | San Jose, CA |
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and route tools: Cadence SOC Encounter, Synopsys ICC - Experience with various congestion relief techniques to achieve high density designs - Experience with taping out chips at... more |
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| May 14 | GSOC Operator | Command Security | San Jose, CA |
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minimum qualifications for assignment to Synopsys include: Minimum HS diploma or equivalent (Some college preferred) Possess valid drivers license Possess a valid First Aid/CPR... more |
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| May 14 | Design Engineer-IEB-Hardware (788263) Job | Microsoft | Mountain View, CA |
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with logic synthesis and timing analysis. Synopsys DC and Primetime experience preferred. - Knowledge of computer architectures desirable. - Knowledge of chip validation and debug... more |
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| May 09 | Sr. CAD Engineer - Verification | Apple | Cupertino, CA |
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SystemVerilog. Must be very experienced with Synopsys VCS, NC-Verilog, or Modelsim. Strong scripting abilities in PERL are needed, TCL or Python is a plus. Good communications... more |
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| May 08 | Senior Physical Design Engineer - FSA | Fujitsu | Sunnyvale, CA |
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design tools (EDI platform). * Experience Synopsys STA tools (Prime Time). * Experience with Mentor Graphics physical verification tools (Calibre). * Prior Tapeout experience. *... more |
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| May 08 | Sr. ASIC Verification Engineer | Synaptics | Santa Clara, CA |
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in using IC simulation tools such as Synopsys VCS * Extensive experience in using synthesis, LEC, and STA tools such as DC, Conformal, and PT * A good understanding of testability... more |
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| May 02 | Engineer, Senior Physical Design | Marvell Technology Group | Santa Clara, CA |
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communication skills. ? Familiar with either Synopsys suite (Astro, Apollo, JupiterXT, Physical Compiler, IC Compiler), Magma suite (BlastFusion, BlastPlan), or Cadence suite... more |
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| May 02 | Physical Design Engineer | Asicsoft | San Jose, CA |
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Physical Design group. Both Cadence and Synopsys flow experience needed. 1- Good understanding of Block P&R 2- Strength in Timing Closure and STA constraints 3- Good Knowledge of... more |
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| May 01 | Staff Engineer - SSD SOC Verification | Western Digital | San Jose, CA |
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he test coverage * Excellent programming skills in System Verilog, C & C++ languages * Experience in CPU based SOC * Skilled with Cadence & Synopsys Simulation tools Job... more |
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| Apr 11 | Intern (Technical) | Synopsys | San Jose, CA |
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This intern will be a member of IT Solutions team working on development and testing of distributed processing framework and visualization tools. The candidate is required to have... more |
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| Apr 11 | Senior Physical Design Engineer | Innovative LOGIC | Santa Clara, CA |
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C designs using synthesis, STA and P&R tools. Must be able to work independently and be a team player Must have 7+ years of experience running Synopsys DC, PT, PTSI and Cadence... more |
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| Apr 09 | US Offer for Physical Design Professionals | Roland & Associates | San Jose, CA |
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synthesis and STA, Static timing analysis,Synopsys ICC, ASIC Implementation, P&R, Cadence encounter, RTL to GDS, RTL to GDSII. Mail your resume to priyank.srivastava@roljobs.com . more |
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| Apr 04 | Clinical Research Associate II | Bayside Solutions | Sunnyvale, CA |
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Our client in the South Bay Area is looking for a Clinical Research Associate II CRA II- Duties: - Responsible for driving and executing day-to-day activities during the conduct... more |
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| Apr 03 | Test Technician, IV | Synopsys | Mountain View, CA |
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Performs memory IP's test chip testing. Support engineering activities for ATE testing, characterization and troubleshooting. Maintain test data base and data process for final... more |
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| Apr 03 | ASIC Physical Design Engineer, Sr. MTS | Altera | San Jose, CA |
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using industry standard EDA tools, such as Synopsys IC Compiler or equivalent * Experience in working with cutting-edge process technology (28nm, 20nm) and taking multiple designs... more |
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| Apr 03 | ASIC Design Engineer | Kelly Services | Santa Clara, CA |
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RTL/Gate Level verification and debug with Synopsys DVE/VCS and/or Modelsim. - 3 years of experience in writing scripts, like Perl/TCL. Preferred Skills and Experience -... more |
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| Mar 29 | Static Timing Analysis Engineer | Samsung | San Jose, CA |
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a fully automated STA scripts/flows using Synopsys PrimeTime Good understanding of deep submicron parasitic effects and newer statistical timing approaches. Good experience in... more |
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| Mar 23 | IC Digital Designer | Cross Creek Systems | Cupertino, CA |
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the entire ASIC design cycle (Verilog, Synopsys Design Compiler, Prime Time, BIST/SCAN insertion, RTL/gate level verification, Back End ASIC or COT model). Should be proficient in... more |
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| Mar 12 | Staff Software Engineer | Xilinx | San Jose, CA |
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simulation tools from Modelsim, Cadence, and Synopsys. Perform functional and timing verification of Xilinx tools using simulation, formal verification and static timing tools. more |
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| Mar 01 | SENIOR EDA/CAD ENGINEER (Synopsys/Cadence) | Terran Systems | San Jose, CA |
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Are you familiar with EDA/CAD tools like Synopsys & Cadence front-end tools/libraries and ... EDA/CAD expertise with Verilog/VHDL and Synopsys library modeling as well as software deve... more |
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| Feb 16 | Member of Technical Staff | Virident | Milpitas, CA |
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Work with the ASIC team to design and develop state of the art tools and verification methodologies for designing Virident System products; perform FPGA design, verification and... more |
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| Feb 08 | Staff Design Verification Engineer | SiRF Technology | Sunnyvale, CA |
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wer design techniques like clock-gating, multi-VDD core/IO domains etc * Good background in DFT, BIST, JTAG/Boundary-Scan and ATPG having experience with either Cadence or... more |
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| Jan 26 | Sr. Applications Engineer | Magma Design Automation | San Jose, CA |
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* Knowledge of industry tools from Synopsys, Cadence, Extreme is a plus. * Experience in 28nm or 40nm tapeout is a plus. * Strong knowledge of scripting languages like Perl,... more |
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| Oct 27 | Digital Staff Design Engineer | Atmel | San Jose, CA |
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synthesis using Cadence RTL compiler or Synopsys Design Compiler * Perform the full spectrum of Digital Design, Verification and Validation, including... more |
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| Sep 15 | CAD / PDK (Process Design Kit) Engineer | SILVACO | Santa Clara, CA |
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circuits * Experience with Layout, DRC/LVS and parasitic extraction tools * Windows and Linux experience * Experience with Cadence, Mentor or Synopsys tools Apply Please quote... more |
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| Jun 02 | SENIOR TAPEOUT MASK DESIGN ENGINEER | NVIDIA | Santa Clara, CA |
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and verification suites (Cadence and Synopsys). - Should also have experience working closely with circuit designers to perform custom layout of complex designs as well as novel... more |
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